1. Field of the Invention
The present invention relates to an image scaling operation device including a coefficient computing circuit that calculates an interpolation coefficient for use in an image scaling process.
2. Description of the Background Art
As disclosed in Japanese Patent Application Laid-Open No. 10-63826 (1998), typical image scaling processors follow the procedure of scaling up an original image to U times and then scaling down the image to 1/D times, to thereby perform a U/D-times arbitrary scaling process, U/D-times including integral multiple as well as a rational multiple. Unfortunately, this method requires the operation for scaling up an original image to U times as well as a memory for storing image data scaled up to U times, resulting in redundant operation and memory.
Japanese Patent Application Laid-Open No. 2000-165664 discloses the technology of directly obtaining a final image (U/D-times image) without obtaining an intermediate image (U-times image) from an original image, which solves the above-mentioned redundancy problem. However, this technology uses a conventional technique for an interpolation process, requiring a divider and a floating point unit.
As described above, the conventional image scaling process requires a divider and a floating point unit, and accordingly, the device configuration becomes complicated.